I said last time I would look at the software and firmware for this post but I decided I needed to spend more time on the regulator to address the DC response issues I had observed, I felt this was more important to get right so this article focuses on that. The good news is, I have achieved good results and I believe the regulator design is complete – at least for the high current version of the module (0-8V 0-8A).
I had problems with the regulator over shooting by about 500mV when transitioning from a high power load to a low power load. There were two main problems, the first was down to the inductance of the wiring on the output, that creates a problem which in turn was amplified by the relatively slow response of the various amplifier stages. I have achieved significant improvement on my previous measurements by tuning response times through the various stages, this simply required lowing the impedance through the various stages to ensure the servo was able to respond more quickly to changes on the output. This was achieved by adding C24, C25, C39, C40, C41, C43, C45, C46, C47 and C48 to the input and driver stages. I also needed to throttle back the fast rise time of the control drive from the DAC to follow behind the response curve of the regulator circuit. These changes mean the regulator now delivers a clean and very acceptable dynamic response to fast-switching load conditions.
The Schematic
Here is the latest schematic which is at version 0.7 including all of the latest changes. The most significant changes are on sheet 3.
I now need to lay out the new PCB and get some ordered, I will do this over the next couple of weeks. I will definitely cover the development environment and the firmware in the next post as well as the serial protocol used to control and monitor the module.
After my initial tests there are two things I now know for sure. The first is I cannot treat the DAC like a programmable voltage source, it’s not going to be accurate enough and secondly, because of the INL of the DAC the resolution needs to be high enough to give me headroom to “trim” the DAC to the correct voltage. On this basis there really are only two practical options to achieve the goal.
The first option is to use a mapping table. Assuming I have a DAC with enough resolution it would be feasible to build some form of calibration rig which could step through each desired voltage then trim the code written to the DAC to get as close as possible for the resolution of the DAC and store that number in a table which can then be written to micro controller as a lookup table. The problem with this approach is its messy, and it would mean that if the calibration was lost in use it would need the calibration rig to re-calibrate it. This is not an ideal solution.
The second option, and the one I will take forward is to build a system where I have an ADC and a DAC and the system is configured so I can read the DAC output. When a given voltage it programmed the ideal DAC code is written to get within a few millivolts of the desired output; and then a software loop is used to trim the DAC code up or down as required to get as close to the required output voltage as possible. If the PSU is to measure up (no pun intended) then it needs a metering function regardless so all I need to do is design the system so I can switch the ADC’s inputs to the DAC for the calibration cycle.
The ADC needs a good resolution, it needs to be accurate and it needs to be low cost. The conversion speed is also important, if its too slow the calibration cycle would take too long to complete. I found a good part for this in the form of the LTC2402 Delta Sigma ADC device from Linear Technologies. I must say at this point that Linear Technologies design support is really great, they have been kind enough to furnish me with sample devices which I have been testing in the design. I have also tested a couple Analog Devices parts too and they were also kind enough to furnish me with sample devices, and these were very close in performance and a bit cheaper too (so not excluded just yet) but for performance in this application Linear Technologies parts so far have the edge – I will talk more about that later on and in future articles because I have tested a few different DAC’s and ADC’s. The following schematic shows the digital control circuitry which is extended to include the ADC chip and a 74HC4053D analogue switch which is used to switch the input of the ADC from monitoring the PSU regulator outputs to monitoring the outputs of the DAC for calibration read-back.
One of the interesting attributes of the ADC chip is it’s a two channel ADC, but in reality though it is actually a single channel ADC with a two channel multiplex on the front end so it samples each channel alternately. This made for an interesting problem to solve because the calibration loop needs the conversions from the ADC to be as fast as possible. The chip its self can only perform a maximum of 6.2 samples per second according to the data sheet, but because of the input multiplexer it can only actually achieve 3.1 samples per second per channel. For normal monitoring three updates per second is acceptable but for calibration I wanted better performance. I configured the analogue switch so in calibration mode I can use both inputs of the ADC to monitor a single channel of the DAC which gives me a calibration loop speed of 6.2 trim and read back per second.
Unlike the DAC, the INL of the ADC is significantly better mainly due to the nature of how it works. The architecture is a switch capacitor system which unlike laser cut resistor strings the charging and discharging of current into a capacitor is significantly more predictable and linear.
https://www.youtube.com/watch?v=f-0m5m7rUQQ PLEASE NOTE: The LED flash is continuous but the video frame rate make it looks like it stopes and starts – which is does not.
In software I have tired two different calibration schemes. The first is the simplest, it sets the ideal code for the target voltage, measures the output of the DAC and does a calculation to determine the difference between the ideal code and the actual code required, then applies this. The second scheme is more complicated. It is the same as the first scheme but then with a second phase of micro trimming which essentially sets a window around the centre point and then adjusts the codes in steps re-reading the output; you can think of this as an electronic/software version of someone turning a variable resistor while watching a meter to get a precise voltage. The second scheme also takes more time as it needs to perform multiple read-backs in order to complete the trim cycle. I have limited the trim cycle to a maximum of eight iterations, in practice it seems to take between 2 and 7 most of the time.
(P.S. The command ‘pr’ means “property read”, it reads the EEPROM configuration of the module)
I re-tested with the spot voltages in the previous blog post and the bottom line is, 14-bits is not enough. The MCP4922 is great for the $$ but its not good enough for this project so I will not bother creating another spot voltage table for this variation, that’s a waste of time given we have established the DAC is just not up to the job. In the next article I will try out two 16-bit DAC chips, one from Analog Devices and the other from Linear Technology.
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