Here is the latest Revison 0.4 schematic which represents the power supply design as described in this blog and videos with the latest round of prototyping and testing.
The headline changes from last time are as follows: –
I have added -Ve supply using a simple charge pump and a PWM drive from the micro controller.
I have added a difference amplifier to correctly handle remote voltage sensing for both PSU voltage control and output voltage read back
I have modified the design to use low-side current sensing instead of high-side current sensing. In doing so I have dropped the use of the high side current sense amp MAX4080 and made use of a spare op amp element instead. This saves a $3 part and replaces it with half of a $2 part
Removed dedicated buffer amp previously added to drive the ADC, the new design removes the need for this because the voltage and current monitoring are better buffered now. This saves another $2 part.
Moved to a faster micro controller PIC18F46K22 which has more memory, more PWM outputs and more I/O pins. No real reason apart from I needed a second PWM output. The firmware is pretty much compatible.
Here is a video overview of the design changes and latest prototype hardware and test setup as well as some basic tests showing load regulation and programmable voltage accuracy benchmarked against a calibrated HP 34401A bench meter.
NOTE: I used a different mic setup and the sound is really poppy and crappy! My apologies…..My dustbin now has a new microphone in it!
Well It’s been over three months since my last post so for those of you that have been following the project I am sorry to have kept you waiting. Work events have taken over recently; I have been really busy and as a result have not had much time to dedicate to the project. I have not been idle though, in those three months I designed and had made two revisions of PCB, have built them up and done lots of testing and as a result now have a clear view of an end design save a for a couple of minor things that still need to be done.
First of all, here is the latest schematic which represents the power supply design as described in this blog and videos with what I believe are the modifications required from the latest round of prototyping and testing.
Here is a video overview of the prototype hardware and test setup as well as some basic tests including load regulation and programmable voltage accuracy benchmarked against a calibrated HP 34401A bench meter.
Here is a video using the software to demonstrate basic set volts, output read-back tests and a benchmark against HP 34401A
I still have the following outstanding issues I want to address before committing effort to laying out a final PCB.
The “Output Off” circuit needs to be verified to resolve the glitch shown in the video when turning the PSU output on
Verify remote sense circuit and approach
Create and test a charge pump to generate a negative supply with a simple regulator, and specifically making sure the diode switching noise does not affect the ADC’s accuracy or stability
Create a minimum load constant current source for the regulator, and deal with measuring output current and compensating for the current source
There is currently no output protection of any kind, I need to deal with reverse polarity input (connect a battery the wrong way around to the input terminals), power feedback (connect a battery the right way around and power down the PSU), connect mains AC voltage into the output terminals. Apart from passing thoughts I have not looked at circuit protection at all.
Verify the accuracy of the current limiting and ADC read-back
In Part 11 I will make further refinements to the design addressing the outstanding items and get a board designed and ordered ready for Part 12 (the final part I hope).
Please do comment and like the videos if you find them interesting. Thank you for watching.
After my initial tests there are two things I now know for sure. The first is I cannot treat the DAC like a programmable voltage source, it’s not going to be accurate enough and secondly, because of the INL of the DAC the resolution needs to be high enough to give me headroom to “trim” the DAC to the correct voltage. On this basis there really are only two practical options to achieve the goal.
The first option is to use a mapping table. Assuming I have a DAC with enough resolution it would be feasible to build some form of calibration rig which could step through each desired voltage then trim the code written to the DAC to get as close as possible for the resolution of the DAC and store that number in a table which can then be written to micro controller as a lookup table. The problem with this approach is its messy, and it would mean that if the calibration was lost in use it would need the calibration rig to re-calibrate it. This is not an ideal solution.
The second option, and the one I will take forward is to build a system where I have an ADC and a DAC and the system is configured so I can read the DAC output. When a given voltage it programmed the ideal DAC code is written to get within a few millivolts of the desired output; and then a software loop is used to trim the DAC code up or down as required to get as close to the required output voltage as possible. If the PSU is to measure up (no pun intended) then it needs a metering function regardless so all I need to do is design the system so I can switch the ADC’s inputs to the DAC for the calibration cycle.
The ADC needs a good resolution, it needs to be accurate and it needs to be low cost. The conversion speed is also important, if its too slow the calibration cycle would take too long to complete. I found a good part for this in the form of the LTC2402 Delta Sigma ADC device from Linear Technologies. I must say at this point that Linear Technologies design support is really great, they have been kind enough to furnish me with sample devices which I have been testing in the design. I have also tested a couple Analog Devices parts too and they were also kind enough to furnish me with sample devices, and these were very close in performance and a bit cheaper too (so not excluded just yet) but for performance in this application Linear Technologies parts so far have the edge – I will talk more about that later on and in future articles because I have tested a few different DAC’s and ADC’s. The following schematic shows the digital control circuitry which is extended to include the ADC chip and a 74HC4053D analogue switch which is used to switch the input of the ADC from monitoring the PSU regulator outputs to monitoring the outputs of the DAC for calibration read-back.
One of the interesting attributes of the ADC chip is it’s a two channel ADC, but in reality though it is actually a single channel ADC with a two channel multiplex on the front end so it samples each channel alternately. This made for an interesting problem to solve because the calibration loop needs the conversions from the ADC to be as fast as possible. The chip its self can only perform a maximum of 6.2 samples per second according to the data sheet, but because of the input multiplexer it can only actually achieve 3.1 samples per second per channel. For normal monitoring three updates per second is acceptable but for calibration I wanted better performance. I configured the analogue switch so in calibration mode I can use both inputs of the ADC to monitor a single channel of the DAC which gives me a calibration loop speed of 6.2 trim and read back per second.
Unlike the DAC, the INL of the ADC is significantly better mainly due to the nature of how it works. The architecture is a switch capacitor system which unlike laser cut resistor strings the charging and discharging of current into a capacitor is significantly more predictable and linear.
https://www.youtube.com/watch?v=f-0m5m7rUQQ PLEASE NOTE: The LED flash is continuous but the video frame rate make it looks like it stopes and starts – which is does not.
In software I have tired two different calibration schemes. The first is the simplest, it sets the ideal code for the target voltage, measures the output of the DAC and does a calculation to determine the difference between the ideal code and the actual code required, then applies this. The second scheme is more complicated. It is the same as the first scheme but then with a second phase of micro trimming which essentially sets a window around the centre point and then adjusts the codes in steps re-reading the output; you can think of this as an electronic/software version of someone turning a variable resistor while watching a meter to get a precise voltage. The second scheme also takes more time as it needs to perform multiple read-backs in order to complete the trim cycle. I have limited the trim cycle to a maximum of eight iterations, in practice it seems to take between 2 and 7 most of the time.
(P.S. The command ‘pr’ means “property read”, it reads the EEPROM configuration of the module)
I re-tested with the spot voltages in the previous blog post and the bottom line is, 14-bits is not enough. The MCP4922 is great for the $$ but its not good enough for this project so I will not bother creating another spot voltage table for this variation, that’s a waste of time given we have established the DAC is just not up to the job. In the next article I will try out two 16-bit DAC chips, one from Analog Devices and the other from Linear Technology.